eng Ansari Education and Research Society Journal of Ultra Scientist of Physical Sciences April 2008 20 1 75 80 jusps-B 1362 article S.G. Modani 1 Rajeev Sharma (monrajanp@rediffmail.com) 2 Parveen Singhal yahparveen_singhal@yahoo.com) 3 Shrutkirti Garg (shrutu_garg2000@yahoo.co.in 3 Govt. Engg. College,.Ajmer (INDIA) Asstt., Prof. ECE, Dept., Vaish College, of Engg. Rohtak (INDIA) Student M.E., Vaish College, of Engg. Rohtak (INDIA) <p style="text-align:justify">Silicon-on-insulator (SOI) wafers are precisely engineered multilayer semiconductor/dielectric structures that provide new functionality for advanced Si devices. It also improves prospects for extending Si devices into the nanometer region (&lt;10 nm channel length). SOI technology possesses many advantages over bulk silicon technology such as reduction of parasitic capacitance, excellent sub-threshold slope, elimination of latch up and resistance to radiation. Hence it is preferred for high speed, high -temperature and low power microelectronic devices. An SOI microchip processing speed is often 30% faster than today&#39;s complementary metal-oxide semiconductor (CMOS)-based chips and power consumption is reduced 80%, which makes them suitable for mobile devices.</p> https://ultraphysicalsciences.org/paper/1362/ Fabrication techniques: SIMOX Smart CutTM